1. Field of the Invention
The present invention relates to a frequency synthesizer, and more particularly, to a frequency synthesizer capable of using a voltage controlled oscillator (VCO) with a low gain Kvco, improving phase noise characteristics, having a short automatic frequency calibration time, and automatically coping with a change of environments.
2. Description of the Related Art
Integrated circuits (ICs) for wireless transceivers are necessarily designed to satisfy conditions of low power consumption and low production cost. In design of such a wireless transceiver satisfying the condition, one of the most important components is a frequency synthesizer. Among various types of conventional frequency synthesizers, fractional-N frequency synthesizers which operate at a high speed are preferred rather than integer-N frequency synthesizers. Here, N is an integer.
FIG. 1 is a block diagram illustrating a conventional fractional-N frequency synthesizer.
Referring to FIG. 1, the conventional fractional-N frequency synthesizer 100 include a reference divider 110, a phase detector 120, a charge pump 130, a loop filter 140, a VCO 150, an automatic frequency calibration block 160, a main divider 170, and two switches S1 and S2.
The reference divider 110 divides a frequency of a reference signal fref with a division ratio of 1/R. Here, R is an integer which is determined based on characteristics of a system in which the frequency synthesizer 100 is used. The system may be a wireless transceiver.
The main divider 170 outputs an output voltage generated by the VCO 150 with a division ratio of 1/(N×P). Here, P is an integer. The main divider 170 includes a pre-scaler 171, a program divider 172, and a sigma-delta (Σ−Δ) modulator 173. The pre-scaler 171 divides a frequency of the output signal Vout with a division ratio of 1/P. The program divider 172 divides a signal output from the pre-scaler 171 with a division ratio of 1/N. The sigma-delta modulator 173 generates the division control signal DC in response to a signal output from the program divider 172. A value of divide number N for the program divider 172 is determined based on the division control signal DC.
The phase detector 120 compares a phase of the signal output form the reference divider 110 and a phase of the signal output from the main divider 170 and outputs a pulse corresponding to a phase difference between the two signals. The charge pump 130 increases or decreases the number of charges according to width and sign of the pulse output from the phase detector 120 to change an output current.
An iteration process for generating the signal fout having a predetermined frequency from the reference signal having the reference frequency fref inevitably causes occurrence of noise components. The loop filter 140 removes the noises occurring during the loop operation. The loop filter 140 includes an array of resisters and capacitors which are serially connected to each other in the loop filter. Therefore, the loop filter 140 can remove the noises included in the output current output from the charge pump 130. In addition, the pumping voltage Vcp is generated by charging or discharging the output current through the capacitors of the loop filter.
The automatic frequency calibration block 160 outputs a frequency control signal AFCout corresponding to a frequency difference between the signal output from the reference divider 110 and the signal output form the main divider 170 and two switch control signals GW1 and GW2. The automatic frequency calibration block 160 includes a frequency detector 161 and a state machine 162. The frequency detector 161 compares the frequency of the signal obtained by the reference divider 110 with a division number of 1/R and the frequency of the signal obtained by the main divider 170 with a division number of 1/(N×P) and outputs a comparison signal corresponding to the frequency difference. The state machine 162 generates the frequency control signal AFCout having information on the frequency fout of the output signal that is to be generated by the VCO 150 and the switch control signal GW1 and GW2 for controlling the two switches S1 and S2 by using the comparison signal output from the frequency detector 161.
The VCO 150 generates an output signal fout in response to a control voltage VC and the frequency control signal AFCout. The control voltage VC is selected from one of the reference voltage Vref and the pumping voltage Vcp output from the loop filter 140 according to a state of the two switches S1 and S2 that are operated by the switch control signals GW1 and GW2 generated from the state machine 162.
As described above, the conventional fractional-N frequency synthesizer 100 performs a general frequency calibration function by using the automatic frequency calibration block 160. The conventional automatic frequency calibration block 160 can calibrate the frequency four of the output signal by using a frequency difference between the signal output from the reference divider 110, that is, a divide-by-R frequency divider and the signal output form the main divider 170, that is, a divide-by-N frequency divider.
In order to reduce the time taken to perform the automatic frequency calibration, the frequency of the signal output from the reference divider 110 needs, to be increased by a multiplication number L (L is an integer). Therefore, a frequency resolution of the banks in the VOC 150 is also increased by the multiplication number L. Accordingly, the steps of the banks are increased. As a result, the gain Kvco of the VCO needs to be increased.
The gain Kvco of the VCO is defined as a ratio of the voltage input to the VCO and the frequency of the output signal. As well-known in the art, the gain Kvco of the VCO is increased, the phase noises are also increased. Namely, in the conventional frequency synthesizer, the phase noise is inevitably increased in order to reduce the time for the automatic frequency calibration.
In addition, one bank included in the VCO is initially determined to be suitable for the environments. Once the one bank is determined, the bank step cannot be changed. Therefore, after the bank is determined, the bank step cannot be modified to be suitable for a change in the environments such as a system or a change in temperature of the system. As a result, the VCO or the frequency synthesizer may be abnormally operated in an actual field.